BUF_WR_READY_STAT_EN=Val_0x0, INT_B_STAT_EN=Val_0x0, INT_C_STAT_EN=Val_0x0, FX_EVENT_STAT_EN=Val_0x0, BGAP_EVENT_STAT_EN=Val_0x0, DMA_INTERRUPT_STAT_EN=Val_0x0, XFER_COMPLETE_STAT_EN=Val_0x0, CMD_COMPLETE_STAT_EN=Val_0x0, CARD_REMOVAL_STAT_EN=Val_0x0, CARD_INTERRUPT_STAT_EN=Val_0x0, INT_A_STAT_EN=Val_0x0, CARD_INSERTION_STAT_EN=Val_0x0, BUF_RD_READY_STAT_EN=Val_0x0
Normal Interrupt Status Enable Register
| CMD_COMPLETE_STAT_EN | Command Complete Status Enable. 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| XFER_COMPLETE_STAT_EN | Transfer Complete Status Enable. 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| BGAP_EVENT_STAT_EN | Block Gap Event Status Enable. 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| DMA_INTERRUPT_STAT_EN | DMA Interrupt Status Enable. 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| BUF_WR_READY_STAT_EN | Buffer Write Ready Status Enable. 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| BUF_RD_READY_STAT_EN | Buffer Read Ready Status Enable. 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| CARD_INSERTION_STAT_EN | Card Insertion Status Enable. 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| CARD_REMOVAL_STAT_EN | Card Removal Status Enable. 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| CARD_INTERRUPT_STAT_EN | Card Interrupt Status Enable. If this bit is set to 0x0, the Host Controller clears the interrupt request to the System. The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 0x1. The Host Driver may clear the Card Interrupt Status Enable before servicing the Card Interrupt and may set this bit again after all interrupt requests from the card are cleared to prevent inadvertent interrupts. By setting this bit to 0x0, interrupt input must be masked by implementation so that the interrupt input is not affected by external signal in any state (for example: floating). 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| INT_A_STAT_EN | INT_A (Embedded) Status Enable. If this bit is set to 0x0, the Host Controller clears the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_A and may set this bit again after all interrupt requests to INT_A pin are cleared to prevent inadvertent interrupts. 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| INT_B_STAT_EN | INT_B (Embedded) Status Enable. If this bit is set to 0x0, the Host Controller clears the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_B and may set this bit again after all interrupt requests to INT_B pin are cleared to prevent inadvertent interrupts. 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| INT_C_STAT_EN | INT_C (Embedded) Status Enable. If this bit is set to 0x0, the Host Controller clears the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_C and may set this bit again after all interrupt requests to INT_C pin are cleared to prevent inadvertent interrupts. 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| FX_EVENT_STAT_EN | FX Event Status Enable. This bit is added from Version 4.10. 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |